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description the avago technologies ADNS-5020-EN is an entry-level, small form factor optical mouse sensor. it comes with many built-in features and optimized for led-based corded products. the ADNS-5020-EN is capable of high-speed motion detection C up to 20 ips and 2g. in addition, it has an on- chip oscillator and built-in led driver to minimize external components. frame rate is also adjusted internally. the ADNS-5020-EN along with the adns-5100/adns- 5100-001 lens, adns-5200 clip and hlmp-ed80 led form a complete and compact mouse tracking system. there are no moving parts, which means high reliability and less maintenance for the end user. in addition, precision optical alignment is not required, facilitating high volume assembly. the sensor is programmed via registers through a three- wire spi interface. it is housed in an 8-pin staggered dual in-line package (dip). theory of operation the ADNS-5020-EN is based on optical navigation tech - nology, which measures changes in position by optically acquiring sequential surface images (frames) and math - ematically determining the direction and magnitude of movement. the ADNS-5020-EN contains an image acquisition system (ias), a digital signal processor (dsp), and a three wire serial port. the ias acquires microscopic surface images via the lens and illumination system. these images are processed by the dsp to determine the direction and distance of motion. the dsp calculates the d x and d y relative displacement values. an external microcontroller reads the d x and d y informa - tion from the sensor serial port. the microcontroller then translates the data into ps2 or usb signals before sending them to the host pc. features ? small form factor ? built-in led driver for simpler circuitry ? high speed motion detection up to 20 ips and 2g ? self-adjusting frame rate for optimum performance ? internal oscillator C no clock input needed ? selectable 500 and 1000 cpi resolution ? operating voltage: 5 v nominal ? three-wire serial interface ? minimal number of passive components applications ? optical mice ? optical trackballs ? integrated input devices ADNS-5020-EN optical mouse sensor data sheet
2 pinout of ADNS-5020-EN optical mouse sensor pin name description 1 sdio serial port data input and output 2 xy_led led control 3 nreset reset pin (active low input) 4 ncs chip select (active low input) 5 vdd5 supply voltage 6 gnd ground 7 rego regulator output 8 sclk serial clock input figure 1. package outline drawing (top view). figure 2. package outline drawing. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. a5020e xyywwz 4.32 (0.170) 9.10 (0.358) 12.85 0.45 (0.506 0.018) notes: 1. dimensions in millimeters (inches). 2. dimensional tolerance: 0.1 mm. 3. coplanarity of leads: 0.1 mm. 4. cumulative pitch tolerance: 0.15 mm. 5. lead pitch tolerance: 0.15 mm. 6. maximum flash: + 0.2 mm. 7. lead width: 0.5 mm. 8. angular tolerance: 3.0 . (at lead tip) 12.85 (0.506) (at shoulder) 0.25 (0.010) pin 1 9.90 (0.390) 0.50 (0.020) lead width 1.00 (0.039) lead offset 2.00 (0.079) lead pitch 5.15 (0.203) 90 3 a5020e xyywwz 4.45 (0.175) 2.00 (0.079) pin 1 4.55 (0.179) 5.60 (0.220) (at base) ? 5.00 (0.197) protective kapton tape ? 0.80 (0.031) clear optical path ?
3 overview of optical mouse sensor assembly avago technologies provides an iges fle drawing de - scribing the base plate molding features for lens and pcb alignment. the ADNS-5020-EN sensor is designed for mounting on a through-hole pcb, looking down. there is an aperture stop and features on the package that align to the lens. the adns-5100/5100-001 lens provides optics for the imaging of the surface as well as illumination of the figure 3. recommended pcb mechanical cutouts and spacing. surface at the optimum angle. features on the lens align it to the sensor, base plate, and clip with the led. the adns-5200 clip holds the led in relation to the lens. the led must be inserted into the clip and the leds leads formed prior to loading on the pcb. the hlmp-ed80 led is recommended for illumination. 2.00 (0.079) 0 (0) 0 (0) 13.06 (0.514) 2.00 (0.079) hole pitch distance 1.37 (0.054) 2.25 (0.089) 10.35 (0.407) 12.85 (0.506) 5.02 (0.198) 6.29 (0.248) 7.56 (0.298) 0.25 (0.010) 26.67 (1.050) 1.00 (0.039) 14.44 (0.569) 6.30 (0.248) 11.22 (0.442) 12.60 (0.496) optional hole for alignment post, if used clear zone all dimensions in millimeters (inches). optical center pin #1 8x ? 0.80 (0.031) 2x ? 0.80 (0.031) 3x ? 3.00 (0.118) 14.94 (0.588) 24.15 (0.951) 25.00 (0.984) 31.50 (1.240)
4 figure 4. 2d assembly drawing of ADNS-5020-EN (top and side views). 13.10 (0.516) 33.45 (1.317) base plate dimensions in mm (inches) 10.58 (0.417) 2.40 (0.094) 7.45 (0.293) top view cross section side view base plate sensor lens pcb top pcb to surface alignment post (optional) navigation surface led clip led bottom of lens flange to surface
5 figure 5. exploded view drawing. pcb assembly considerations 1. insert the sensor and all other electrical components into pcb. 2. insert the led into the assembly clip and bend the leads 90 degrees. 3. insert the led clip assembly into pcb. 4. wave solder the entire assembly in a no-wash solder process utilizing solder fxture. the solder fxture is needed to protect the sensor during the solder process. it also sets the correct sensor-to-pcb distance as the lead shoulders do not normally rest on the pcb surface. the fxture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. 5. place the lens onto the base plate. 6. remove the protective kapton tape from optical aperture of the sensor. care must be taken to keep contaminants from entering the aperture. recommend not to place the pcb facing up during the entire mouse assembly process. recommend to hold the pcb frst vertically for the kapton removal process. 7. insert pcb assembly over the lens onto the base plate aligning post to retain pcb assembly. the sensor aperture ring should self-align to the lens. figure 6. block diagram of ADNS-5020-EN optical mouse sensor. 8. the optical position reference for the pcb is set by the base plate and lens. note that the pcb motion due to button presses must be minimized to maintain optical alignment. 9. i n s t a l l m o u s e to p c a s e. th e re m u s t b e a feature in the top case to press down onto the pcb assembly to ensure all components are interlocked to the correct vertical height. adns-5100 (lens) customer supplied pcb hlmp-ed80 (led) adns-5200 (led clip) sensor customer supplied base plate with recommended alignment features per iges drawing power and control serial port and registers image array dsp oscillator led drive rego gnd vdd5 ncs ADNS-5020-EN sclk sdio nreset xy_led
6 design considerations for improved esd performance for improved electrostatic discharge performance, typical creepage and clearance distance are shown in the table below. assumption: base plate construction as per the avago technologies supplied iges fle and adns-5100/5100-001 lens. note that the lens material is polycarbonate or polysty - rene hh30, therefore, cyanoacrylate based adhesives or other adhesives that may damage the lens should not be used. figure 7. sectional view of pcb assembly highlighting optical mouse components. typical distance millimeters creepage 16.0 clearance 2.1 lens/light pipe base plate surface sensor led clip pcb
7 figure 8. schematic diagram for interface between ADNS-5020-EN and microcontroller. v cc v cc v cc v cc v dd v cc q1 2 1 3 r3 27k r4 27k r2 240 d2 z-led qa qb c4 3.3 c3 0.1 c2 4.7 c1 0.1 d1 hlmp -ed80 7 2 6 xy_led gnd reg0 xy_led sclk sdio ncs nreset 8 1 4 3 z-encoder +5v 5 ADNS-5020-EN u1 p1.0 p1.1 p1.2 p1.3 p1.6 p1.7 p0.7 p0.6 p0.5 p0.4 p0.2 p0.3 p1.4 p1.5 p0.0 p0.1 vpp mc u with usb features gnd xout vreg xin/p2.1 r13 1.30k d+/sclk d ? /sda t 1 2 3 4 v bus gnd d+ d ? power j1 sw 2 sw 1 sw 3 middle right left c7 0.1 recommended led bin: bin p and above (p , q, r, s....)
8 regulatory requirements ? passes fcc b and worldwide analogous emission limits when assembled into a mouse with shielded cable and following avago technologies recommendations. ? passes iec-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and following avago technologies recommendations. ? passes en61000-4-4/iec801-4 eft tests when assembled into a mouse with shielded cable and following avago technologies recommendations. ? ul fammability level ul94 v-0. ? provides sufcient esd creepage/clearance distance to avoid discharge up to 15 kv when assembled into a mouse using adns-5100 round lens according to usage instructions above. recommended operating conditions parameter symbol minimum typical maximum units notes operating temperature t a 0 40 c power supply v dd 4.0 5.0 5.25 v power supply rise time v rt 0.005 100 ms 0 to v dd supply noise (sinusoidal) v na 100 mv p-p 10 khz-50 mhz serial port clock frequency f sclk 1 mhz 50% duty cycle. distance from lens reference z 2.3 2.4 2.5 mm plane to tracking surface (z) speed s 16 20 ips acceleration a 2 g load capacitance c out 100 pf sdio absolute maximum ratings parameter symbol minimum maximum units notes storage temperature t s -40 85 c lead solder temp 260 c supply voltage v dd -0.5 5.5 v esd 2 kv all pins, human body model mil 883 method 3015 input voltage v in -0.5 v dd +0.5 v all i/o pins output current iout 7 ma sdio pin figure 9. distance from lens reference plane to tracking surface (z). 2.40 (0.094) z = object surface sensor lens lens reference plane
9 ac electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25 c, v dd = 3.3 v. parameter symbol minimum typical maximum units notes power down t pd 50 ms from pd (when bit 1 of register 0x0d is set) to low current wake from power down t wakeup 50 55 ms from pd inactive (when nreset pin is asserted high or write 0x5a to register 0x3a) to valid motion reset pulse width t reset 250 ns active low. motion delay after reset t mot-rst 50 ms from nreset pull high to valid mo tion, assuming v dd and motion is present. sdio rise time t r-sdio 150 300 ns c l = 100pf sdio fall time t f-sdio 150 300 ns c l = 100pf sdio delay after sclk t dly-sdio 120 ns from sclk falling edge to sdio data valid, no load conditions. sdio hold time t hold-sdio 0.5 1/f sclk us data held until next falling sclk edge. sdio setup time t setup-sdio 120 ns from data valid to sclk rising edge. spi time between t sww 30 s from rising sclk for last bit of the frst write commands data byte, to rising sclk for last bit of the second data byte. spi time between write t swr 20 s from rising sclk for last bit of the frst and read commands data byte, to rising sclk for last bit of the second address byte. spi time between read t srw 500 ns from rising sclk for last bit of the frst and subsequent commands t srr data byte, to falling sclk for the frst bit of the next address. spi read address-data delay t srad 4 s from rising sclk for last bit of the address byte, to falling sclk for frst bit of data being read. ncs inactive after motion burst t bexit 250 ns minimum ncs inactive time after motion burst before next spi usage. ncs to sclk active t ncs-sclk 120 ns from ncs falling edge to frst sclk rising edge. sclk to ncs inactive t sclk-ncs 120 ns from last sclk rising edge to ncs (for read operation) rising edge, for valid sdio data transfer. sclk to ncs inactive t sclk-ncs 20 us from last sclk rising edge to ncs (for write operation) rising edge, for valid sdio data transfer. ncs to sdio high-z t ncs-sdio 500 ns from ncs rising edge to sdio high-z state. transient supply current i ddt 60 ma max supply current during a v dd ramp from 0 to v dd .
10 dc electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25 c, v dd = 3.3 v. parameter symbol minimum typical maximum units notes dc supply current i dd_avg 6 10 ma average sensor current, at max frame rate. no load on sdio. idle supply current 2 ma input low voltage v il 0.5 v sclk, sdio, ncs, nreset input high voltage v ih v dd C 0.5 v sclk, sdio, ncs, nreset input hysteresis v i_hys 200 mv sclk, sdio, ncs, nreset input leakage current i leak 1 10 a vin = vdd-0.6 v, sclk, sdio, ncs, nreset xy_led current i xy_led 20 50 ma average current at maximum frame rate. xy_led pin voltage range should be greater than 0.8 v. output low voltage v ol 0.7 v i out = 1 ma, sdio output high voltage v oh vdd-0.7 v i out = -1 ma, sdio input capacitance c in 50 pf ncs, sclk, sdio, nreset typical performance characteristics figure 10. mean resolution vs. distance from lens reference plane to surface. figure 11. average error vs. distance (mm). figure 12. relative wavelength responsivity. normalized response 400 0 wavelength (nm) 900 1.0 0.4 0.5 0.6 0.7 0.8 0.9 0.3 700 800 1000 0.1 0.2 600 500
11 led mode for power savings, the led will not be continuously on. ADNS-5020-EN will pulse the led only when needed. synchronous serial port the synchronous serial port is used to set and read parameters in the ADNS-5020-EN, and to read out the motion information. the port is a three wire serial port. the host micro-con - troller always initiates communication; the ADNS-5020-EN never initiates data transfers. sclk, sdio, and ncs may be driven directly by a micro-controller. the port pins may be shared with other spi slave devices. when the ncs pin is high, the inputs are ignored and the output is tri-stated. the lines that comprise the spi port: sclk: clock input. it is always generated by the master (the micro-controller). sdio: input and output data. ncs: chip select input (active low). ncs needs to be low to activate the serial port; otherwise, sdio will be high z, and sdio & sclk will be ignored. ncs can also be used to reset the serial port in case of an error. write operation sdio setup and hold time chip select operation the serial port is activated after ncs goes low. if ncs is raised during a transaction, the entire transaction is aborted and the serial port will be reset. this is true for all transactions. after a transaction is aborted, the normal address-to-data or transaction-to-transaction delay is still required before beginning the next trans - action. to improve communication reliability, all serial transactions should be framed by ncs. in other words, the port should not remain enabled during periods of non-use because esd and eft/b events could be inter - preted as serial communication and put the chip into an unknown state. in addition, ncs must be raised after each burst-mode transaction is complete to terminate burst-mode. the port is not available for further use until burst-mode is terminated. write operation write operation, defned as data going from the micro- controller to the ADNS-5020-EN, is always initiated by the micro-controller and consists of two bytes. the frst byte contains the address (seven bits) and has a 1 as its msb to indicate data direction. the second byte contains the data. the ADNS-5020-EN reads sdio on rising edges of sclk. 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 d 0 d 5 d 6 d 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 1 a 6 d 4 d 3 d 2 d 1 sclk ncs sdio sdio driven by micro-controller t setup 1/ f sclk 1/ f sclk t hold sclk sdio
12 read operation a read operation, defned as data going from the adns- 5020-en to the micro-controller, is always initiated by the micro-controller and consists of two bytes. the frst byte contains the address, is sent by the micro- con - troller over sdio, and has a 0 as its msb to indicate data direction. the second byte contains the data and is driven by the ADNS-5020-EN over sdio. the sensor outputs sdio bits on falling edges of sclk and samples sdio bits on every rising edge of sclk. read operation microcontroller to ADNS-5020-EN handof ADNS-5020-EN to microcontroller handof note: the 0.5/f sclk minimum high state of sclk is also the minimum sdio data hold time of the ADNS-5020-EN. since the falling edge of sclk is actually the start of the next read or write command, the ADNS-5020-EN will hold the state of data on sdio until the falling edge of sclk. 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d 0 d 5 d 6 d 7 a 0 a 1 a 2 a 3 a 4 a 5 a 6 d 4 d 3 d 2 d 1 sclk cycle # sclk sdio sdio driven by micro-controller sdio driven by ADNS-5020-EN det ail "a" det ail "b" d 7 d 6 a 0 a 1 det ail "a" microcontroller to ADNS-5020-EN sdio handoff sdio sclk t setup t srad t hold 0 ns, min. t dl y 0 ns, min. t dl y hi-z d 0 t dl y t hold r/w bit of next address sclk sdio det ail "b" ADNS-5020-EN to microcontroller sdio handoff driven by micro released by 5020
13 required timing between read and write commands there are minimum timing requirements between read and write commands on the serial port. if the rising edge of the sclk for the last data bit of the second write command occurs before the required delay (t sww ), then the frst write command may not complete correctly. timing between two write commands if the rising edge of sclk for the last address bit of the read command occurs before the required delay (t swr ), the write command may not complete correctly. timing between write and read commands during a read operation sclk should be delayed at least t srad after the last address data bit to ensure that the ADNS-5020-EN has time to prepare the requested data. the falling edge of sclk for the frst address bit of either the read or write command must be at least t srr or t srw after the last sclk rising edge of the last data bit of the previous read operation. timing between read and either write or subsequent read commands sclk t sw w write operation address data write operation address data sclk t sw r write operation address data next read operation address ? ? ? ? ? ? sclk t srad read operation address next read or write operation address ? ? ? ? ? ? t srw & t srr data
14 notes on power-up and reset the ADNS-5020-EN does not perform an internal power up self-reset; the nreset pin must be asserted low every time power is applied. there are two ways to reset the chip, either assert low nreset pin or by writing 0x5a to register 0x3a. a full reset will thus be executed. any register settings must then be reloaded. burst mode operation burst mode is a special serial port operation mode that may be used to reduce the serial transaction time for a motion read. the speed improvement is achieved by con - tinuous data clocking to or from multiple registers without the need to specify the register address, and by not requiring the normal delay period between data bytes. burst mode is activated by reading the motion_burst register. the ADNS-5020-EN will respond with the contents of the delta_x, delta_y, squal, shutter_ upper, shutter_lower, maximum_pixel and pixel_sum registers in that order. the burst transaction can be terminated anywhere in the sequence after the delta_x value by bringing the ncs pin high. after sending the register address, the micro-controller must wait t srad and then begin reading data. all data bits can be read with no delay between bytes by driving sclk at the normal rate. the data are latched into the output bufer after the last address bit is received. after the burst transmission is complete, the micro-controller must raise the ncs line for at least t bexit to terminate burst mode. the serial port is not available for use until it is reset with ncs, even for a second burst transmission. avago technologies highly recommends the usage of burst mode operation in optical mouse sensor design applica - tions. motion burst timing motion_burst register address read first byte first read operation read second byte read third byte sclk ? ? ? ? ? ? t srad notes on power down the ADNS-5020-EN can be set in power down mode by setting bit 1 of register 0x0d. in addition, the spi port should not be accessed during power down. (other ics on the same spi bus can be accessed, as long as the sensors ncs pin is not asserted.) the table below shows the state of various pins during power down. there are 2 ways to exit power down, either assert low nreset pin or by writing 0x5a to register 0x3a. a full reset will thus be executed. wait twakeup before accessing the spi port. any register settings must then be reloaded. pin power down active nreset functional ncs functional* sdio functional* sclk functional* xy_led low current * ncs pin must be held to 1(high) if spi bus is shared with other devices. it can be in either state if the sensor is the only device in addition to the controller microprocessor. note: there is long wakeup time from power down. the feature should not be used for power management during normal mouse motion. during power-up there will be a period of time after the power supply is high but before any clocks are available. the table below shows the state of the various pins during power-up and reset. state of signal pins after vdd is valid pin during reset after reset ncs ignored functional sdio ignored depends on ncs sclk ignored depends on ncs xy_led hi-z functional
15 registers the ADNS-5020-EN registers are accessible via the serial port. the registers are used to read motion data and status as well as to set the device confguration. address register read/write default value 0x00 product_id r 0x12 0x01 revision_id r 0x01 0x02 motion r 0x00 0x03 delta_x r any 0x04 delta_y r any 0x05 squal r any 0x06 shutter_upper r any 0x07 shutter_lower r any 0x08 maximum_pixel r any 0x09 pixel_sum r any 0x0a minimum_pixel r any 0x0b pixel_grab r/w any 0x0c reserved 0x0d mouse control r/w 0x00 0x0e C 0x39 reserved 0x3a chip_reset w n/a 0x3b C 0x3e reserved 0x3f inv_rev_id r 0xfe 0x40 C 0x62 reserved 0x63 motion_burst r 0x00
16 motion address: 0x02 access: read/write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field mot reserved reserved reserved reserved reserved reserved reserved data type: bit feld. usage: register 0x02 allows the user to determine if motion has occurred since the last time it was read. if the mot bit is set, then the user should read registers 0x03 and 0x04 to get the accumulated motion. read this register before reading the delta_x and delta_y registers. writing anything to this register clears the mot bit, delta_x and delta_y registers. the written data byte is not saved. field name description mot motion since last report 0 = no motion 1 = motion occurred, data ready for reading in delta_x and delta_y registers reserved reserved product_id address: 0x00 access: read reset value: 0x12 bit 7 6 5 4 3 2 1 0 field pid 7 pid 6 pid 5 pid 4 pid 3 pid 2 pid 1 pid 0 data type: 8-bit unsigned integer usage: this register contains a unique identifcation assigned to the ADNS-5020-EN. the value in this register does not change; it can be used to verify that the serial communications link is functional. revision_id address: 0x01 access: read reset value: 0x01 bit 7 6 5 4 3 2 1 0 field rid 7 rid 6 rid 5 rid 4 rid 3 rid 2 rid 1 rid 0 data type: 8-bit unsigned integer usage: this register contains the ic revision. it is subject to change when new ic versions are released.
17 delta_x address: 0x03 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 data type: eight bit 2s complement number. usage: x movement is counts since last report. absolute value is determined by resolution. reading clears the register. note: avago technologies recommends that registers 0x03 and 0x04 be read sequentially. 80 81 fe ff 00 01 02 7e 7f -128 -127 -2 -1 0 + 1 + 2 +126 +127 motion del t a_x delta_y address: 0x04 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 data type: eight bit 2s complement number. usage: y movement is counts since last report. absolute value is determined by resolution. reading clears the register. note: avago technologies recommends that registers 0x03 and 0x04 be read sequentially. 80 81 fe ff 00 01 02 7e 7f -128 -127 -2 -1 0 + 1 + 2 +126 +127 motion del t a_y
18 data type: upper 8 bits of a 9-bit unsigned integer. usage: squal (surface quality) is a measure of the number of valid features visible by the sensor in the current frame. the maximum squal register value is 144. since small changes in the current frame can result in changes in squal, variations in squal when looking at a surface are expected. the graph below shows 250 sequentially acquired squal values, while a sensor was moved slowly over white paper. squal is nearly equal to zero, if there is no surface below the sensor. squal is typically maximized when the navigation surface is at the optimum distance from the imaging lens (the nominal z- height). figure 13. squal values (white paper). figure 14. mean squal vs. z (white paper). squal address: 0x05 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field sq 7 sq 6 sq 5 sq 4 sq 3 sq 2 sq 1 sq 0
19 shutter_upper address: 0x06 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 shutter_lower address: 0x07 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 data type: sixteen bit unsigned integer. usage: units are clock cycles. read shutter_upper frst, then shutter_lower. they should be read con - secutively. the shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. the shutter value is automatically adjusted. figure 15. shutter (white paper). figure 16. mean shutter vs. z (white paper).
20 maximum_pixel address: 0x08 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field mp 0 mp 6 mp 5 mp 4 mp 3 mp 2 mp 1 mp 0 data type: eight-bit number. usage: maximum pixel value in current frame. minimum value = 0, maximum value = 127. the maximum pixel value can vary with every frame. pixel_sum address: 0x09 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 data type: high 8 bits of an unsigned 15-bit integer. usage: this register is the accumulated pixel value from the last image taken. the maximum accumulator value is 28,575, but only bits [14:7] are reported. it may be described as the full sum divided by 1.76. the maximum register value is 223. the minimum is 0. the pixel sum value can change on every frame.
21 minimum_pixel address: 0x0a access: read reset value: 0x00 data type: eight-bit number. usage: minimum pixel value in current frame. minimum value = 0, maximum value = 127. the minimum pixel value can vary with every frame. pixel_grab address: 0x0b access: read/write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field valid pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 data type: eight-bit word. usage: the pixel grabber captures 1 pixel per frame. if there is a valid pixel in the grabber when this register is read, the msb will be set, an internal counter will incremented to capture the next pixel and the grabber will be armed to capture the next pixel. it will take 225 reads to upload the complete image. any write to this register will reset and arm the grabber to grab pixel 0 on the next image. bit 7 6 5 4 3 2 1 0 field mp 0 mp 6 mp 5 mp 4 mp 3 mp 2 mp 1 mp 0
22 physical pixel address map C readout order of the array (looking through the sensor aperture at the bottom of the package) lb rb positive x positive y top x-ray view of mouse positive x positive y bottom view of mouse hole at mouse bottom cover for lens a5020 xyywwz vdd5 5 gnd 6 reg0 7 sclk 8 4 ncs 3 nreset 2 xy_led 1 sdi o 14 29 44 59 74 89 104 119 134 149 164 179 194 209 224 13 28 43 58 73 88 103 118 133 148 163 178 193 208 223 12 27 42 57 72 87 102 117 132 147 162 177 192 207 222 11 26 41 56 71 86 101 116 131 146 161 176 191 206 221 10 25 40 55 70 85 100 115 130 145 160 175 190 205 220 9 2 4 3 9 5 4 6 9 8 4 9 9 1 14 129 144 159 174 189 204 219 8 2 3 3 8 5 3 6 8 8 3 9 8 1 13 128 143 158 173 188 203 218 7 2 2 3 7 5 2 6 7 8 2 9 7 1 12 12 7 1 42 157 172 187 202 217 6 2 1 3 6 5 1 6 6 8 1 9 6 1 11 12 6 1 41 156 171 186 201 216 5 2 0 3 5 5 0 6 5 8 0 9 5 1 10 12 5 1 40 155 170 185 200 215 4 1 9 3 4 4 9 6 4 7 9 9 4 1 09 12 4 1 39 154 169 184 199 214 3 1 8 3 3 4 8 6 3 7 8 9 3 1 08 12 3 1 38 153 168 183 198 213 2 1 7 3 2 4 7 6 2 7 7 9 2 1 07 12 2 1 37 152 167 182 197 212 1 1 6 3 1 4 6 6 1 7 6 9 1 1 06 12 1 1 36 151 166 181 196 211 0 1 5 3 0 4 5 6 0 7 5 9 0 1 05 12 0 1 35 150 165 180 195 210 first pixel last pixel
reserved address: 0x0c mouse_control address: 0x0d access: read/write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field reserved reserved reserved reserved reserved reserved pd res data type: eight bit number usage: mouse sensor resolution and power down settings can be accessed or to be edited by this register. reserved address: 0x0e-0x39 chip_reset address: 0x3a access: write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field cr 7 cr 6 cr 5 cr 4 cr 3 cr 2 cr 1 cr 0 data type: 8-bit unsigned integer usage: write 0x5a to initiate chip reset. field name description pd power down 0 = normal 1 = power down res set resolution 0 = 500 cpi 1 = 1000 cpi reserved reserved
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 2007 avago technologies limited. all rights reserved. obsoletes av01-0327en av02-0365en - august 8, 2007 reserved address: 0x3b C 0x3e inv_rev_id address: 0x3f access: read reset value: 0xfe bit 7 6 5 4 3 2 1 0 field rrid 7 rrid 6 rrid 5 rrid 4 rrid 3 rrid 2 rrid 1 rrid 0 data type: 8-bit unsigned integer usage: this register contains the inverse of the revision id which is located at register 0x01. reserved address: 0x40-0x62 motion_burst address: 0x63 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field mb 7 mb 6 mb 5 mb 4 mb 3 mb 2 mb 1 mb 0 data type: various. usage: read from this register to activate burst mode. the sensor will return the data in the delta_x, delta_y, squal, shutter_upper, shutter_lower, maximum_pixel and pixel_sum. if the burst is not terminated at this point, the internal address counter stops incrementing and pixel sum registers value will be continuously returned. bursts are terminated when ncs is raised.

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